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ARTS-NVM Publications

2025

ARTS-NVM A
Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications

Jörg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Seidl, Kuan Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, Ming-Liang WeiProceedings of the 43rd IEEE/ACM International Conference on Computer-Aided DesignAssociation for Computing Machinery2025Invited Paper.
10.1145/3676536.3697114 [BibTex]

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BibTex Entry

@inproceedings{Henkel:2025,
author = {Henkel, Jörg and Siddhu, Lokesh and Nassar, Hassan and Bauer, Lars and Chen, Jian-Jia and Hakert, Christian and Seidl, Tristan and Chen, Kuan Hsun and Hu, Xiaobo Sharon and Li, Mengyuan and Yang, Chia-Lin and Wei, Ming-Liang},
booktitle = {Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design},
date = {2025-04-09},
doi = {10.1145/3676536.3697114},
eid = {125},
eventdate = {2024-10-27},
isbn = {9798400710773},
location = {New York, NY, USA},
note = {Invited Paper},
publisher = {Association for Computing Machinery},
series = {ICCAD '24},
title = {Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications},
venue = {Newark Liberty International Airport Marriott, New York, NY, USA},
}

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ARTS-NVM
Evaluating the Impact of Racetrack Memory Misalignment Faults on BNNs Performance

Leonard David Bereholschi, Mikail Yayla, Jian-Jia Chen, Kuan-Hsun Chen, Asif Ali KhanEmbedded Computer Systems: Architectures, Modeling, and SimulationSpringer Nature Switzerland2025.
10.1007/978-3-031-78377-7_16 [BibTex]

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BibTex Entry

@inproceedings{Bereholschi:2025,
abstract = {Racetrack memory ({RTM}) is a promising non-volatile memory ({NVM}) technology that offers exceptional density, power and performance benefits over other {NVM} and conventional memory technologies. {RTM} cells have the unique capability of storing hundreds of data bits per cell and are equipped with one or more access ports. However, accessing data in an {RTM} cell requires the data to be shifted and aligned to an access port, introducing performance and energy overheads and potentially leading to misalignment faults. A misalignment fault occurs when after the shift operation, the desired data is not properly aligned to an access port and incorrect data is read from the {RTM} cell. Countermeasures have been proposed to mitigate the effects of these faults on applications’ accuracy, albeit at the cost of increased overhead. There is potential to balance the trade-offs between acceptable drops in accuracy and enhancements in performance, especially in error-resilient applications such as Binarized Neural Networks ({BNNs}). However, there exists no tool that enables effective exploration of this design space and assess the potential trade-offs.},
author = {Bereholschi, Leonard David and Yayla, Mikail and Chen, Jian-Jia and Chen, Kuan-Hsun and Ali Khan, Asif},
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
date = {2025},
doi = {10.1007/978-3-031-78377-7_16},
editor = {Carro, Luigi and Regazzoni, Francesco and Pilato, Christian},
isbn = {9783031783777},
keywords = {Binarized neural networks ({BNNs}), Racetrack memory, Reliability, Accuracy, Misalignment Faults},
langid = {english},
location = {Cham},
pages = {230–245},
publisher = {Springer Nature Switzerland},
series = {SAMOS 2024},
title = {Evaluating the Impact of Racetrack Memory Misalignment Faults on {BNNs} Performance},
}

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Conference ARTS-NVM B
Hardware/Software Co-Analysis for Worst Case Execution Time Bounds

Can Joshua Lehmann, Lars Bauer, Hassan Nassar, Heba Khdr, Jörg HenkelDesign, Automation & Test in Europe Conference (DATE)IEEE2025.
10.23919/date64628.2025.10992765 [BibTex]

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BibTex Entry

@inproceedings{Lehmann:2025,
author = {Lehmann, Can Joshua and Bauer, Lars and Nassar, Hassan and Khdr, Heba and Henkel, Jörg},
booktitle = {Design, Automation \& Test in Europe Conference (DATE)},
date = {2025},
doi = {10.23919/date64628.2025.10992765},
entrysubtype = {Conference},
pages = {1-2},
publisher = {IEEE},
title = {Hardware/Software Co-Analysis for Worst Case Execution Time Bounds},
}

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Conference ARTS-NVM B
REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based Attacks

Hassan Nassar, Ming-Liang Wei, Chia-Lin Yang, Jörg Henkel, Kuan-Hsun ChenDesign, Automation & Test in Europe Conference (DATE)IEEE2025.
10.23919/date64628.2025.10992747 [BibTex]

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BibTex Entry

@inproceedings{Nassar:2025a,
author = {Nassar, Hassan and Wei, Ming-Liang and Yang, Chia-Lin and Henkel, Jörg and Chen, Kuan-Hsun},
booktitle = {Design, Automation \& Test in Europe Conference (DATE)},
date = {2025},
doi = {10.23919/date64628.2025.10992747},
entrysubtype = {Conference},
pages = {1-2},
publisher = {IEEE},
title = {REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based Attacks},
}

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ARTS-NVM
Turbo-FHE: Accelerating Fully Homomorphic Encryption with FPGA and HBM Integration

Hassan Nassar, Lars Bauer, Jörg HenkelIEEE Design & Test42.32025.
10.1109/MDAT.2025.3527368 [BibTex]

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BibTex Entry

@article{Nassar:2025,
abstract = {The landscape of {IT} infrastructure shifted with the adoption of cloud computing, allowing organizations to use on-demand services, relieving them from owning {IT} infrastructure. However, this transformation comes with escalating concerns over privacy and security as the data processing is done on plaintext. If the cloud provider is malicious or vulnerable, the data of the users can be breached [1].},
author = {Nassar, Hassan and Bauer, Lars and Henkel, Jörg},
date = {2025-01-10},
doi = {10.1109/MDAT.2025.3527368},
eventtitle = {{IEEE} Design \& Test},
issn = {2168-2364},
journaltitle = {{IEEE} Design \& Test},
keywords = {Field programmable gate arrays, Polynomials, Noise, Homomorphic encryption, Arrays, Memory management, Accuracy, Three-dimensional displays, Bandwidth, Software},
number = {3},
pages = {86–93},
shorttitle = {Turbo-{FHE}},
title = {Turbo-{FHE}: Accelerating Fully Homomorphic Encryption with {FPGA} and {HBM} Integration},
url = {https://ieeexplore.ieee.org/document/10836861/},
volume = {42},
}

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2024

ARTS-NVM
An FPGA-Based RISC-V Instruction Set Extension and Memory Controller for Multi-Level Cell NVM

Mina Ibrahim, Martel Shokry, Lokesh Siddhu, Lars Bauer, Hassan Nassar, Jörg Henkel2024 International Conference on Microelectronics (ICM)2024ISSN: 2159-1679.
10.1109/ICM63406.2024.10815826 [BibTex]

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BibTex Entry

@inproceedings{Ibrahim:2024,
abstract = {Non-volatile memory ({NVM}) technologies, particularly Multi-Level Cell ({MLC}) {NVMs}, offer significant potential for increasing memory density. {MLC} {NVMs} provide a trade-off between write latency and retention time, where faster writes/stores result in lower retention and slower writes yield higher retention. However, limited work has been done to validate and prototype {NVM}-based systems in hardware, leveraging this tradeoff at the system level. In this paper, we present a novel memory controller architecture and a {RISC}-V instruction set extension to optimize {MLC} {NVM} write operations by balancing speed and retention time. Our custom {NVM} controller, built around a finite state machine with an {AXI} memory-mapped interface, efficiently manages read/write operations with enhanced burst transfers, minimizing latency. Additionally, we introduce a fast-store instruction in {RISC}-V to increasing write performance while addressing retention limitations. These enhancements are implemented in hardware on an {FPGA} platform. Experimental results show that our controller reduces hardware overhead by 30\% compared to conventional designs, and the fast-store instruction improves performance by over 7\% for streaming workloads with less than 0.08\% hardware overhead.},
author = {Ibrahim, Mina and Shokry, Martel and Siddhu, Lokesh and Bauer, Lars and Nassar, Hassan and Henkel, Jörg},
booktitle = {2024 International Conference on Microelectronics ({ICM})},
date = {2024-12},
doi = {10.1109/ICM63406.2024.10815826},
eventtitle = {2024 International Conference on Microelectronics ({ICM})},
issn = {2159-1679},
keywords = {Nonvolatile memory, Instruction sets, Microprocessors, Automata, Prototypes, Hardware, Delays, Microelectronics, Optimization, Clocks, {NVM}, {FPGA}, {RISC}-V},
note = {{ISSN}: 2159-1679},
pages = {1–6},
title = {An {FPGA}-Based {RISC}-V Instruction Set Extension and Memory Controller for Multi-Level Cell {NVM}},
url = {https://ieeexplore.ieee.org/document/10815826},
}

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ARTS-NVM
Towards Enabling Synchronous Releases for Periodic Tasks in RTEMS

Tristan Seidl, Mario Günzel, Jian-Jia Chen, Kuan-Hsun ChenProceedings of OSPERT 2024. The 18th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications2024.
[BibTex]

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BibTex Entry

@inproceedings{Seidl:2024,
author = {Tristan Seidl and Mario Günzel and Jian-Jia Chen and Kuan-Hsun Chen},
booktitle = {Proceedings of OSPERT 2024. The 18th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications},
date = {2024-07-09},
location = {Lille, France},
pages = {13–18},
pubstate = {published},
series = {OSPERT 2024},
title = {Towards Enabling Synchronous Releases for Periodic Tasks in RTEMS},
url = {https://www.ecrts.org/wp-content/uploads/2024/07/ospert24-proceedings.pdf},
venue = {Lille, France},
year = {2024},
}

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ARTS-NVM
Towards Enabling Synchronous Releases for Periodic Tasks in RTEMS

Tristan Seidl, Mario Günzel, Jian-Jia Chen, Kuan-Hsun ChenThe 18th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT)2024.
[BibTex]

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BibTex Entry

@inproceedings{Seidl:2024a,
author = {Seidl, Tristan and Günzel, Mario and Chen, Jian-Jia and Chen, Kuan-Hsun},
booktitle = {The 18th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT)},
date = {2024},
title = {Towards Enabling Synchronous Releases for Periodic Tasks in RTEMS},
url = {https://www.ecrts.org/wp-content/uploads/2024/07/ospert24-proceedings.pdf},
}

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Workshop ARTS-NVM MD
Towards Non-Volatile Memory Wear-Leveling In (Timing)-Critical Systems

Christian Hakert, Kay Heider, Junjie Shi, Jian-Jia Chen2nd Workshop on OPtimization for Embedded and ReAl-time systems (OPERA)2024.
[BibTex]

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BibTex Entry

@inproceedings{Hakert:2024,
author = {Hakert, Christian and Heider, Kay and Shi, Junjie and Chen, Jian-Jia},
booktitle = {2nd Workshop on OPtimization for Embedded and ReAl-time systems (OPERA)},
date = {2024},
entrysubtype = {Workshop},
title = {Towards Non-Volatile Memory Wear-Leveling In (Timing)-Critical Systems},
url = {https://opera24.di.unito.it/wp-content/uploads/2024/11/1_Final_version.pdf},
}

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2023

ARTS-NVM
Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory

Nils Hölscher, Christian Hakert, Hassan Nassar, Kuan-Hsun Chen, Lars Bauer, Jian-Jia Chen, Jörg HenkelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems42.82023.
10.1109/TCAD.2022.3228897 [BibTex]

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BibTex Entry

@article{Hoelscher:2023a,
abstract = {Emerging nonvolatile memory yields, alongside many advantages, technical shortcomings, such as reduced cell lifetime. Although many wear-leveling approaches exist to extend the lifetime of such memories, usually a tradeoff for the granularity of wear leveling has to be made. Due to iterative write schemes (repeatedly sense and write), wear out of memory in certain systems is directly dependent on the written bit value and thus can be highly imbalanced, requiring dedicated bit-wise wear leveling. Such a bit-wise wear leveling so far has only be proposed together with a special hardware support. However, if no dedicated hardware solutions are available, especially for commercial off-the-shelf systems with nonvolatile memories, a software solution can be crucial for the system lifetime. In this work, we propose entirely software-based bit-wise wear leveling, where the position of bits within {CPU} words in the main memory is rotated on a regular basis. We leverage the {LLVM} intermediate representation to adjust load and store operations of the application with a custom compiler pass. Experimental evaluation shows that the lifetime by applying local rotation within the {CPU} word can be extended by a factor of up to 21{\\}times . We also show that our method can incorporate with coarser-grained wear leveling, e.g., on block granularity and assist achievement of higher lifetime improvements.},
author = {Hölscher, Nils and Hakert, Christian and Nassar, Hassan and Chen, Kuan-Hsun and Bauer, Lars and Chen, Jian-Jia and Henkel, Jörg},
date = {2023-08},
doi = {10.1109/TCAD.2022.3228897},
eventtitle = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
issn = {1937-4151},
journaltitle = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
keywords = {Nonvolatile memory, Memory management, Iterative methods, Computer architecture, Microprocessors, Synchronization, Hardware, Bit rotation, intermediate representation ({IR}), {LLVM}, nonvolatile main memory, wear leveling},
number = {8},
pages = {2527–2539},
shorttitle = {Memory Carousel},
title = {Memory Carousel: {LLVM}-Based Bitwise Wear Leveling for Nonvolatile Main Memory},
url = {https://ieeexplore.ieee.org/document/9984978},
volume = {42},
}

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ARTS-NVM MD
Rapid NVM Simulation and Analysis on Single Bit Granularity Featuring Gem5 and NVMain

Nils Hölscher, Minh Duy Truong, Christian Hakert, Tristan Seidl, Kuan-Hsun Chen, Jian-Jia Chen2023 IEEE 12th Non-Volatile Memory Systems and Applications Symposium (NVMSA)2023ISSN: 2575-257X.
10.1109/NVMSA58981.2023.00012 [BibTex]

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BibTex Entry

@inproceedings{Hoelscher:2023,
abstract = {In emerging computing systems, non-volatile memory ({NVM}) is becoming an alternative to conventional main memory technologies such as {DRAM}. With its many advantages it also yields disadvantages, such as shorter memory cell life times. Due to its shorter lived nature, wear-leveling on main memory becomes an important aspect of systems using {NVM}. Hardware methods are implemented such as iterative write schemes (repeatedly sense and write), which will check a memory cell before changing it. But hardware methods alone do not provide optimal wear-leveling, so they should be used together with software based methods, which try to evenly distribute wear over large memory regions. However, for software wear leveling on {NVM} main memory no standardized evaluation setup exists. Which leaves most of these approaches incomparable to each other. In this work we will leverage existing solutions for evaluation such as Gem5 [1] and {NVMain} [20] and extend them with our own methods, analysis setup and benchmark suite. We thoroughly explain our setup in this article and provide a tool for a comparable and easy to use evaluation setup for software based {NVM} main memory wear-leveling.},
author = {Hölscher, Nils and Truong, Minh Duy and Hakert, Christian and Seidl, Tristan and Chen, Kuan-Hsun and Chen, Jian-Jia},
booktitle = {2023 {IEEE} 12th Non-Volatile Memory Systems and Applications Symposium ({NVMSA})},
date = {2023-08},
doi = {10.1109/NVMSA58981.2023.00012},
eventtitle = {2023 {IEEE} 12th Non-Volatile Memory Systems and Applications Symposium ({NVMSA})},
issn = {2575-257X},
keywords = {Measurement, Nonvolatile memory, Random access memory, Benchmark testing, Software, Hardware, Iterative methods, Simulation, Non-Volatile Memory, Wear-Out, Benchmark, Tool, Wear-Leveling},
note = {{ISSN}: 2575-257X},
pages = {50–55},
title = {Rapid {NVM} Simulation and Analysis on Single Bit Granularity Featuring Gem5 and {NVMain}},
url = {https://ieeexplore.ieee.org/document/10254342},
}

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Special Session ARTS-NVM HYPNOS CIMware HetCIM B
Special Session – Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications

Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi Tahoori, Mahta Mayahinia, Jeronimo Castrillon, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun ChengProceedings of the 2023 International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES)2023.
10.1145/3607889.3609088 [BibTex]

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BibTex Entry

@inproceedings{Henkel:2023,
author = {Henkel, Jörg and Siddhu, Lokesh and Bauer, Lars and Teich, Jürgen and Wildermann, Stefan and Tahoori, Mehdi and Mayahinia, Mahta and Castrillon, Jeronimo and Khan, Asif Ali and Farzaneh, Hamid and de Lima, João Paulo C. and Chen, Jian-Jia and Hakert, Christian and Chen, Kuan-Hsun and Yang, Chia-Lin and Cheng, Hsiang-Yun},
booktitle = {Proceedings of the 2023 International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES)},
comment-marcel = {SPP grant CIMware missing},
date = {2023-09},
doi = {10.1145/3607889.3609088},
entrysubtype = {Special Session},
location = {Hamburg, Germany},
pages = {11-20},
pubstate = {published},
title = {Special Session – Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications},
}

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ARTS-NVM
Swift-CNN: Leveraging PCM Memory's Fast Write Mode to Accelerate CNNs

Lokesh Siddhu, Hassan Nassar, Lars Bauer, Christian Hakert, Nils Hölscher, Jian-Jia Chen, Jörg HenkelIEEE Embedded Systems Letters (ESL)15.42023.
10.1109/LES.2023.3298742 [BibTex]

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BibTex Entry

@article{Siddhu:2023,
author = {Siddhu, Lokesh and Nassar, Hassan and Bauer, Lars and Hakert, Christian and Hölscher, Nils and Chen, Jian-Jia and Henkel, Jörg},
date = {2023-09-25},
doi = {10.1109/LES.2023.3298742},
journaltitle = {IEEE Embedded Systems Letters (ESL)},
number = {4},
pages = {234-237},
pubstate = {published},
title = {Swift-CNN: Leveraging PCM Memory's Fast Write Mode to Accelerate CNNs},
volume = {15},
year = {2023},
}

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MD ARTS-NVM C
Towards Data-Based Cache Optimization of B+-Trees

Roland Kühn, Daniel Biebert, Christian Hakert, Jian-Jia Chen, Jens TeubnerProceedings of the 19th International Workshop on Data Management on New Hardware, DaMoN 2023, Seattle, WA, USA, June 18-23, 2023ACM2023.
10.1145/3592980.3595316 [BibTex]

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BibTex Entry

@inproceedings{Kuehn:2023,
author = {Roland Kühn and Daniel Biebert and Christian Hakert and Jian-Jia Chen and Jens Teubner},
booktitle = {Proceedings of the 19th International Workshop on Data Management on New Hardware, DaMoN 2023, Seattle, WA, USA, June 18-23, 2023},
date = {2023},
doi = {10.1145/3592980.3595316},
editor = {Norman May and Nesime Tatbul},
pages = {63–69},
publisher = {ACM},
pubstate = {published},
title = {Towards Data-Based Cache Optimization of B+-Trees},
}

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